In a typical computer system, a mass storage disk device is usually utilized to store data that are frequently transferred to or from the host system. In such data transfer processes between the host and the disk device, the operations are either a host write disk cycle or a host read disk cycle. Furthermore, to accommodate different data transfer characteristics of both the host and the disk, a buffer memory is commonly utilized to temporarily hold the data during the transfer process.
During the host read disk cycle for instance, the data recorded on the disk magnetic medium are sensed and transferred out through the disk controller to a buffer memory first and then further to the host when the host is ready to receive the data. During the host write disk cycle, data coming from the host are sent to the buffer memory first and then to the disk controller and finally enter into the disk.
In either direction of the data transfer cycle, a direct memory access (DMA) controller of the disk controller is used to control all transfer actions involved. First of all, the host accesses the buffer memory in units of data bytes while the data readout or written into the disk are in the units of sectors (512 bytes for example). Hence, the DMA controller must ascertain whether the buffer memory is empty or full when the host is to transfer data on the one hand, and to assure that there is a complete sector of data to be written into the disk. Also, the DMA controller must ensure that there is a full sector space available in the buffer memory for data to be read out from the disk.
Furthermore, the DMA controller generates address signals that are necessary for the host and the disk controller to access a specific buffer memory location so that the data can be transferred to or from the buffer memory. In addition, the DMA controller must prevent the host from reading data back from the disk when some errors have emerged and have not been corrected.
There exist many techniques in buffer arrangements interfacing the host and mass storage devices. For instances, U.S. Pat. No. 3,851,335 discloses a simple up/down counter to keep track of the data transfer to and from a buffer. For a read out operation, the counter is decremented while simultaneous input and read out do not affect the counter. This is too simple a device to tackle the problems a sophisticated DMA controller must solve.
U.S. Pat. No. 4,723,233 discloses a DMA controller that includes several address registers to indicate beginning and end addresses defining a transfer area of a disk, a location counter which points to an accessed area, and an updating circuit to set a location counter to the initial address after reaching the end address. The purpose of this technique is to reduce the loss of speed of transfer.
There are also well known implementations of different DMA control functions in several commercial disk controllers. For instance, Adaptec Inc.'s disk controller (AIC-610) incorporates a DMA controller which has pointers designated as write access, read access and stop pointers. The actual uses of the first two pointers depend upon which buffer port is selected and the direction of data transfer. The stop pointer is used to control data transfer between the host and the buffer. In this approach, transfer control processes are performed by the host, thereby reducing the host's performance.
The other known design of a DMA controller is Standard Microsystems Corp.'s disk controller (95CO2). In this device, the DMA controller is enhanced to a level equivalent to a microprocessor, including many internal registers, counters, a state machine and an ALU (arithmetic and logic unit). Its various counters include an offset counter to keep track of the empty/full condition in the buffer and an auxiliary offset counter to trace the number of error-free data bytes left in the buffer. Although the DMA controller allows disk data transfers without the intervention of the host, the controller itself requires much additional hardware and involves complex operations.